1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, it relates to a method of fabricating a semiconductor device having an element isolation region.
2. Description of the Background Art
In general, a method of forming a deep trench for isolating a high concentration impurity layer in a substrate in addition to element isolation through a field oxide film formed by a LOCOS (local oxidation of silicon) method is known as an element isolation technique for a semiconductor device such as a bipolar transistor. However, the field oxide film formed by the LOCOS method is disadvantageously inferior in surface flatness, and hard to refine due to increase of the area of an element isolation region resulting from a bird's beak.
In place of the LOCOS method, therefore, there has recently been proposed an element isolation technique employing STI (shallow trench isolation) presenting excellent flatness and allowing further refinement. For example, Japanese Patent Laying-Open No. 9-8119 (1997) discloses such an element isolation technique employing STI.
FIGS. 17 to 27 are sectional views for illustrating conventional fabrication processes for a semiconductor device including element isolation regions according to STI. The conventional fabrication processes for a semiconductor device are now described with reference to FIGS. 17 to 27.
As shown in FIG. 17, an N+-type buried layer 102 is formed on the main surface of a P-type silicon substrate 101. An N-type epitaxial silicon layer 103 is formed on the N+-type buried layer 102. A silicon oxide film (SiO2 film) 104 is formed on the N-type epitaxial silicon layer 103 by thermal oxidation. An Si3N4 film 105 is formed on the silicon oxide film 104 for serving as a stopper film in a CMP (chemical mechanical polishing) step described later. A resist film 106 is formed on a prescribed region of the Si3N4 film 105.
Thereafter the resist film 106 is employed as a mask for dry-etching the Si3N4 film 105 and the silicon oxide film 104, and the epitaxial silicon layer 103 is thereafter partially etched thereby forming shallow trenches 120 to enclose the element forming region 150, as shown in FIG. 18. Thereafter the resist film 106 is removed.
As shown in FIG. 19, an HDP-NSG (high density plasma non-doped silicate glass) film 107 having an excellent embedding property is formed on the overall surface by high density plasma CVD (HDP-CVD). Thereafter the Si3N4 film 105 is employed as a stopper film for removing an excess depositional portion of the HDP-NSG film 107 by CMP, thereby forming HDP-NSG films 107 having flat upper surfaces embedded in the shallow trenches 120 as shown in FIG. 20.
As shown in FIG. 21, another Si3N4 film 108 is formed on the HDP-NSG films 107 and the Si3N4 film 105 for serving as a stopper film in another CMP step described later. A silicon oxide film (SiO2 film) 109 is formed on the Si3N4 film 108 by CVD. Resist films 110 are formed on prescribed regions of the silicon oxide film 109.
As shown in FIG. 22, the resist films 110 are employed as masks for etching the silicon oxide film 109, the Si3N4 film 108 and the HDP-NSG films 107 thereby patterning the same. Thereafter the resist films 110 are removed for obtaining a shape shown in FIG. 23.
As shown in FIG. 24, the silicon oxide film 109 is employed as a hard mask for etching the n-type epitaxial silicon layer 103, the N+-type buried layer 102 and the P-type silicon substrate 101, thereby forming deep trenches 130 for isolating the N+-type buried layer 102. Thereafter the silicon oxide film 109 is removed thereby obtaining a shape shown in FIG. 25.
As shown in FIG. 26, a silicon oxide film (SiO2 film) 111 is formed by CVD to fill up the deep trenches 130 while extending on the Si3N4 film 108. Thereafter the Si3N4 film 108 is employed as a stopper film for removing an excess depositional portion of the silicon oxide film 111 by CMP, followed by removal of the Si3N4 films 108 and 105 and the silicon oxide film 104. The surfaces of the HDP-NSG films 107 are also scraped when the silicon oxide film 104 is removed, whereby element isolation regions having flat upper surfaces are finally formed as shown in FIG. 27.
The element isolation regions employed for a conventional bipolar transistor (semiconductor device) are formed in the aforementioned manner. Thereafter the bipolar transistor (not shown) is formed on the element forming region 150.
In the conventional method of fabricating a semiconductor device including element isolation regions shown in FIGS. 17 to 27, however, the excess depositional portion of the HDP-NSG films 107 filling up the shallow trenches 120 and those of the silicon oxide films 111 filling up the deep trenches 130 are removed through different CMP steps respectively, disadvantageously leading to complicated fabrication processes. Further, the Si3N4 films 105 and 108 must be formed for serving as stopper films in the respective CMP steps, also disadvantageously leading to complicated fabrication processes. In addition, the fabrication cost is increased due to the two CMP steps requiring high unit costs.